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Features
* 2nd Generation EE Complex Programmable Logic Devices
- 3.0V to 3.6V Operating Range with 5V Tolerant I/Os - 32 - 512 Macrocells with Enhanced Features - Pin-compatible with Industry-standard Devices - Speeds to 4.5 ns Maximum Pin-to-pin Delay - Registered Operation to 225 MHz Enhanced Macrocells with Logic DoublingTM Features - Bury Either Register or COM while Using the Other for Output - Dual Independent Feedback Allows Multiple Latch Functions per Macrocell - 5 Product Terms per Macrocell, Expandable to 40 per Macrocell with Cascade Logic, Plus 15 More with Foldback Logic - D/T/Latch Configurable Flip-flops plus Transparent Latches - Global and/or per Macrocell Register Control Signals - Global and/or per Macrocell Output Enable - Programmable Output Slew Rate per Macrocell - Programmable Output Open Collector Option per Macrocell - Fast Registered Input from Product Term Enhanced Connectivity - Single Level Switch Matrix for Maximum Routing Options - Up to 40 Inputs per Logic Block Advanced Power Management Features - ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and I/O for A Level Standby Current on "L" versions - Pin-controlled 1 mA Standby Mode - Reduced-power Option per Macrocell - Automatic Power Down of Unused Macrocells - Programmable Pin-keeper Inputs and I/Os Available in Commercial and Industrial Temperature Ranges Available in All Popular Packages Including PLCC, PQFP, TQFP and BGA EE Technology - 100% Tested - Completely Reprogrammable - 10,000 Program/Erase Cycles - 20 Year Data Retention - 2000V ESD Protection - 200 mA Latch-up Immunity JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993 - Pull-up Option on JTAG Pins TMS and TDI IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG PCI-compliant Security Fuse Feature
*
ATF15XXAE Family Datasheet ATF1502AE(L) ATF1504AE(L) ATF1508AE(L) ATF1516AE(L) ATF1532AE(L) Preliminary
* *
* * *
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Rev. 2398E-12/01
1
General Description
Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells in 1996, Atmel's CPLD products have delivered extra IO connectivity and logic reusability. Atmel's commitment to efficient, flexible architecture has continued with the current Atmel ATF15xx Family of industry-standard, pin-compatible CPLDs. Atmel's Logic Doubling architecture consists of wider fan-in, additional routing and clock options, combined with sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel enhanced macrocell includes double independent buried feedback that allows designers to pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for later revisions. The Atmel ATF15xx family delivers enhanced functionality and flexibility with no additional design effort and is highly cost effective. The Atmel ATF15xx Family includes all popular configurations and speeds. Table 1. ATF15XXAE Family Device Features
Feature Usable Gates Macrocells Logic Blocks Max. # Pins Max. User I/Os TPD Grades (ns) ATF1502AE(L) ATF1504AE(L) ATF1508AE(L) ATF1516AE(L) ATF1532AE(L)
750 32 2 44 36 4, 7, 10(15)
1500 64 4 100 68 4, 7, 10(15)
3000 128 8 256 100 5, 7, 10(15)
6000 256 16 256 164 5, 7, 10(15)
12000 512 32 256 212 5, 7, 12(15)
The Atmel ATF15XXAE Family includes pin-compatible products in all popular packages. Table 2. ATF15XXAE Family Device Packages and Number of Signal Pins(1)(2)
Packages 44-pin PLCC 44-pin TQFP 49-ball BGA 84-pin PLCC 100-pin TQFP 100-ball BGA 144-pin TQFP 169-ball BGA 208-pin PQFP 256-ball BGA 100 68 68 ATF1502AE(L) 36 36 ATF1504AE(L) 36 36 41 68 84 84 100 100 164 164 176 212 84 84 120 120 ATF1508AE(L) ATF1516AE(L) ATF1532AE(L)
Notes:
1. Contact Atmel for up-to-date information on device and package availability. 2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing (BST), the four associated pins become JTAG pins and are unavailable for user I/O.
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Functional Description
The ATF15XXAE Family of 3.3 Volt supply, high-performance, high-density complex programmable logic devices (CPLDs) utilizes Atmel's proven electrically-erasable technology. With up to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF15XXAE Family's enhanced macrocell architecture, switch matrices and routing increase usable gate count for new designs and increase odds of successful pin-locked design modifications while maintaining pin-compatibility with industry-standard CPLDs. The ATF15XXAE Family devices have four dedicated input pins and depending on the type of device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each input and I/O pin also feeds into the global bus. The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in each logic block selects 40 individual signals from the global bus. Macrocells within a given logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic between macrocells in the Logic Block allows fast, efficient generation of complex logic functions. All macrocells are capable of being I/Os; however, the actual number of I/O pins depends on the device and package type. The ATF15XXAE Family members contain two, four, eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a fan-in of 40 inputs from the switch matrix having access to up to 80 product terms. Unused macrocells are automatically disabled by the fitter software to decrease power consumption. A security fuse, when programmed, protects the contents of the other fuses. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. The ATF15XXAE Family devices are In-System Programmable (ISP) devices. They use the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with JTAG's Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.
Global Bus/Switch Matrix
The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback signals from all macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Up to 40 of these signals can be selected as inputs to the individual logic blocks by the fitter software. Atmel's ATF15xx Family of CPLDs use a single level switch matrix signal distribution structure, where each logic block input has access to the same number of global bus inputs, maximizing the number of possible ways to route a global bus signal. This single level structure is in contrast with split switch matrix structures used by others in which routing a particular global bus input to a particular logic block input makes that signal unavailable to some other logic blocks, thus greatly limiting the available opportunities to route. The ATF15XXAE Family macrocell, shown in Figure 2, consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can generate a foldback logic term from the product term mux and a buried feedback with extra routing that go to the global bus.
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Figure 1. ATF15XXAE Family Typical Block Diagram
2 to 16 N
2 to 16
N-1
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Figure 2. ATF15XXAE Family Macrocell with Enhanced Features In Red
SWITCH REGIONAL MATRIX FOLDBACK OUTPUTS BUS CASIN
80
16
LOGIC FOLDBACK
SWITCH MATRIX
40
PT1 PT2 1 PT3
GOE[0:5] 6
Product Term MUX
2
Q !Q AP I/O Pin D/T*/L Q I/O Pin
3
4
CK/CK/LE GCK[0:2] 3 CE SLEW RATE AR !Q OPEN COLLECTOR
GOE SWITCH MATRIX
GOE [0:5]
5 PT4 PT5
GCLEAR
GLOBAL BUS
Reduced Power Option CASOUT * T flip-flop synthesised
Product Terms and Select Mux
Within each macrocell are five product terms. Each product term may receive as its inputs any combination of the signals from the switch matrix or regional foldback bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the fitter software, which selects the optimum macrocell configuration. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The macrocell's XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JKtype flip-flops, or fed to the buried feedback to synthesize an extra latch.
OR/XOR/ CASCADE Logic
Foldback Bus
Each macrocell can also generate a foldback product term. This signal goes to the regional bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse polarity of one of the macrocell's product terms. Although Cascade Logic is the preferred method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms in each region can also generate additional fan-in sum terms with nominal additional delay.
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Flip-flop
The ATF15XXAE Family's flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output or vice-versa. (This enhanced function is automatically implemented by the fitter software). The flip-flop can be configured for D, T, JK and SR operation, and changes state on the clock's rising edge. It can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. When a GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop has asynchronous reset and preset. The flip-flop's asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off.
Output Buffer
The ATF15XXAE Family macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. (This enhanced function is automatically implemented by the fitter software) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell. The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configuration, all the macrocell resources are still available, including the buried feedback, expander and CASCADE logic. The output enable for each macrocell can be selected as one of six global OE signals or a product term. In addition, some product term feedbacks can generate one of the global output enables. The buffer has a fast/slow slew rate option to control EMI and an open-collector option which enables the device to provide control signals such as an interrupt that can be asserted by any of the several devices.
Programmable Pin-keeper Option for Inputs and I/Os
The ATF15XXAE Family offers the option of programming all input and I/O pins with pin-keeper circuits enabled. When any pin is driven high or low and then subsequently left floating, the pin keeper circuit will hold it at that previous high or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The pin-keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.
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Input Diagram
PROGRAMMABLE OPTION (PIN KEEPER)
I/O Diagram
PROGRAMMABLE OPTION (PIN KEEPER)
Speed/Power Management
Multiple Power Supplies, Power Sequencing and Hot-Socketing
The ATF15XXAE Family has several speed and power management features.
Because the ATF15XXAE Family can be used in a system with mixture of power supply voltages, it has been designed to function with the VCCINT and VCCIO power supplies applied in any sequence. Also, until the power up sequence completes, the input/output buffers are kept in a high impedance state, and so may be driven but do not drive power out.
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Power-on Reset
The ATF15xx Family devices are designed with a power-on reset, a feature critical for state machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. The clock must remain stable during TD. The ATF15xx Family has two options for the hysteresis about the reset level, VRST, Small and Large. To ensure a robust operating environment in applications where the device is operated near 3.0V, Atmel recommends that during the fitting process users configure the device with the Power-on Reset hysteresis set to Large.
Power Down of Unused Macrocells Input Transition Detection/ Automatic Power Down
To conserve power, Atmel fitters automatically power down all unused macrocells.
The ATF15XXAEL versions provide automatic power down to A level standby power (the "L" suffix indicates "low" power) through Atmel's patented Input Transition Detection (ITD) circuitry on Global Clocks, Inputs and I/O. These ITD circuits automatically put the device into a lowpower standby mode when no logic transitions are occurring. This reduces power consumption during inactive periods, and so provides proportional power-savings for most applications running at system speeds below fcritical (~5 MHz). In clocked applications where the device is operated at a frequency high enough to keep the device from going into standby (above fcritical), the device will perform at the faster speeds given in the next faster speed column. These higher speeds can be achieved in combinatorial designs as well, as long as, once activated by an initial input transition, the device continues to receive input transitions often enough to keep the device from going into standby mode again. That is, the time between input transitions is less than 1/fcritical.
Reduced-Power per Macrocell
To further reduce power, each ATF15xx Family macrocell has a reduced-power bit feature. With this feature the designer can reduce power by 50% or more for logic that does not need to operate at the maximum switching speed. The reduced-power bit may be activated by changing the default OFF to ON for any or all macrocells. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced- power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. All power-down AC characteristic parameters are computed from external input or I/O pins, with the reducedpower bit turned on. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching. The slew rate option is selected in the design source file. All ATF15xx Family devices also have an optional pin-controlled power-down mode. When activated, one or both of two pins, PD1 and PD2, can act as power-down pins. The device goes into power-down when either PD1 or PD2 pins (or both) are high, and the device supply current is reduced to less than 1 mA. Also, all internal logic signals are latched and held, as are any enabled outputs. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. Input and I/O hold
Slew Rate Control
Pin Controlled Power-down
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latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. All pin transitions are ignored until the PD pin is brought low. When the powerdown feature is enabled for PD1 or PD2, that pin cannot be used as a logic input or output. However, the pin's macrocell may still be used to generate buried foldback and cascade logic signals. The power-down option is selected in the design source file.
Power Consumption Estimates
An estimate of power consumption can be made based on typical designs and operation conditions, but because it is sensitive to these factors, power consumption must be verified with actual pattern and operation conditions. The equations given below are based on a pattern of 16-bit up/down counters in each logic block and may be used to estimate power consumption for both operating modes. 1. Pstandby = Iccstandby x Vsupply Where: Iccstandby = the standby current given for the particular device and standby mode (e.g., pin controlled Power Down) Vsupply= the power supply voltage
Standby Power
Active Power
2. Pactive = Pinternal + Pload = Iccinternal x Vsupply + Pload Where: Iccinternal = the internal current estimated from equation 3 below Vsupply= the power supply voltage Pload = depends on the device output load capacitance and switching frequency on each output pin. Pload and additional power savings at low frequencies using Atmel Input Transition Detection ("L" versions) can be estimated according to the methods discussed in the Atmel Application Note "Saving Power with Atmel PLDs" 3. Iccinternal = [K1 x (MCinuse - MCreducedpower )] + (K2 x MCreducedpower) + (K3 x MCinuse x fop x NS) Where: MCreducedpower = the number of macrocells operating at reduced power (from fitter report file) MCinuse= the number of macrocells in use (from fitter report file. Unused macrocells are powered down.) NS = the proportion of logic nodes switching (typically 10-20%) fop = the switching frequency K1, K2,and K3 = device constants given in the table below.
Device ATF1502AE ATF1504AE ATF1508AE ATF1516AE ATF1532AE Note: K1 0.6 0.6 0.6 0.6 0.6 K2 0.3 0.3 0.3 0.3 0.3 K3 0.015 0.015 0.015 0.015 0.015
Shaded data is preliminary and subject to change without notice.
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Design Software
Atmel ATF15xx Family fitters allow logic synthesis using a variety of high-level description languages and formats. ATF15xx Family designs are supported by Atmel specific design tools as well as by several third-party tools. Free conversion software is also offered for industry standard devices. Check the Atmel web site or contact your authorized Atmel sales representative for up-to-date design software information. ATF15xx Family devices can be programmed using standard third-party programmers. With third-party programmers, the JTAG ISP port can be disabled thereby allowing four additional I/O pins to be used for logic. Check the Atmel web site, contact your authorized Atmel sales representative or Atmel PLD Applications for details of third-party programmers. ATF15xx Family devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF15xx Family via the PC. ISP is performed by using either a download cable, a compatible board tester or a simple microprocessor interface. It is most common to devote the JTAG pins to ISP, but it is possible to use ISP to program the part through the JTAG pins, and set these four pins I/O pins. However, this will effectively disable further ISP and the device will need to be erased on a programmer to re-enable ISP. Contact Atmel PLD Applications by e-mail at pld@atmel.com or call our Hotline at (408) 4364333 for details. To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by the Atmel ISP software. Conversion to other ATE tester formats is also possible. Check the Atmel web site for up-to-date programming and software support information.
Programming
ISP Programming Protection
The ATF15xx Family also incorporates a protection feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper option preserves the former state during device programming. All ATF15xx Family devices are initially shipped in the erased state thereby making them ready to use for ISP. For more information refer to the "Designing for In-System Programmability with Atmel CPLDs" application note.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF15xx Family fuse patterns. Once programmed, fuse verify is inhibited. However, the User Signature and device ID remain accessible.
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JTAG-BST Overview
The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP) controller. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own Boundary-scan Cell (BSC) in order to support boundary-scan testing. The ATF15XXAE Family does not currently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The ATF15xx Family implements six BST instructions, and seven Atmel-defined In System Programming (ISP) instructions. All ATF15xx Family BST and ISP instructions have a length of 10 bits.
JTAG BST Instructions SAMPLE/PRELOAD EXTEST Description Captures signals at the device pins for later examination, or loads a data pattern prior to an EXTEST instruction. Allows testing of off-chip circuitry and interconnections by forcing a pattern on the output pins or capturing signals from the input pins. Places a single shift register stage between TDI and TDO, allowing test BST data to pass through a particular device in a chain of devices. Places the 32-bit IDCODE register between TDI and TDO, allowing the IDCODE data to be shifted out of TDO. Places the 16-bit user electronic signature register between TDI and TDO, allowing the UESCODE data to be shifted out of TDO. Places the BYPASS register between TDI and TDO in a high impedance mode, protecting the device from damage from externally applied test signals. These seven instructions allow in-system programming via the four JTAG pins.
BYPASS
IDCODE
UESCODE
HIGHZ
7 ISP instructions
The ATF15xx Family BST implementation complies with the Boundary-scan Definition Language (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be used to perform BST on the ATF15xx Family. The ATF15xx Family also has the option of using four JTAG-standard I/O pins for in-system programming (ISP). The ATF15xx Family is programmable through the four JTAG pins using programming-compatible with the IEEE JTAG Standard 1149.1. Programming is performed by using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. Refer to Atmel Application Note "Designing for In-System Programmability with Atmel CPLDs for more details.
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JTAG Boundary-scan Cell (BSC) Testing
The ATF15xx Family has four dedicated input pins and a number of I/O pins depending on the device type and package type selected. Each input pin and I/O pin has a boundary-scan cell (BSC) which supports boundary-scan testing as described in detail by IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the (BST) capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller.
Boundary-Scan Register Length 96 192 352 672 1232 IDCODE MSB LSB 0000,0001,0101,0100,0010,0000,0011,1111 0000,0001,0101,0100,0100,0000,0011,1111 0000,0001,0101,0100,1000,0000,0011,1111 0000,0001,0101,0101,0000,0000,0011,1111 0000,0001,0101,0110,0000,0000,0011,1111
Device ATF1502AE ATF1504AE ATF1508AE ATF1516AE ATF1532AE Note:
Shaded data is preliminary and subject to change without notice.
Boundary-scan Definition Language (BSDL) Models
These are now available in all package types via the Atmel web site. These models conform to the IEEE 1149.1 standard and can be used for Boundary-scan Test Operation of the ATF15xx Family.
The BSC configuration for the input and I/O pins and macrocells are shown below.
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BSC Configuration for Pins (Except JTAG TAP Pins)
.
BSC Configuration for Macrocell
TDO OEJ
0 0 1 1 DQ DQ
OUTJ
0 0 1 1 DQ DQ
Pin
Capture Register TDI Shift
Update Register Mode Clock
Macrocell BSC
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PCI Compliance
The ATF15xx Family also supports peripheral component interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers.
2.4
Voltage
PCI Voltage-tocurrent Curves for +5V Signaling in Pull-up Mode
Pull Up
VCC
Test Point
1.4
DC drive point
AC drive point
-2
-44 Current (mA) -178
2.2
DC drive point
0.55
Test Point
Voltage
PCI Voltage-tocurrent Curves for +5V Signaling in Pull-down Mode
Pull Down
VCC
AC drive point
3.6
95 Current (mA) 380
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Timing Model
U
Pin Capacitance
Typ(1) CIN CI/O Note: Max 8 Units pF Condition VIN = 0V; f = 1.0 MHz
8 pF VOUT = 0V; f = 1.0 MHz 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.
Input Test Waveforms and Measurement Levels
Output AC Test Loads
3.3V (2.5V) 703 (521 ) 8060 (481 ) C = CL
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Absolute Maximum Ratings*
Ambient Temperature Under Bias.................. -65C to +135C Storage Temperature ..................................... -65C to +150C Junction Temperature ..............................................150C(MAX) Voltage on Any Pin with Respect to Ground .......................................-2.0V to +5.75V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) DC Output Current per Pin ................................ -25 to +25 mA Note: *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. For currents less than 100 mA, minimum voltage is -0.6 VDC and maximum voltage is VCC + 0.75 VDC. Pulses of less than 20s may undershoot to -2.0V or overshoot to 5.75V.
DC and AC Operating Conditions
Commercial Operating Temperature (Ambient), TA Junction Temperature, TJ
(1)
Industrial -40C - 85C - 3.0V - 3.6V 3.0V - 3.6V 2.3V - 2.7V -0.5V - 5.75V 0 - VCCIO 40 ns Max 40 ns Max
0C - 70C - 3.0V - 3.6V 3.0V - 3.6V 2.3V - 2.7V -0.5V - 5.75V 0 - VCCIO 40 ns Max 40 ns Max
VCCINT (3.3V) Power Supply VCCIO (3.3V) Power Supply VCCIO (2.5V) Power Supply VI Input Voltage VO Output Voltage tR Input Rise Time tF Input Fall Time Note:
1. Junction temperature is package and device dependant and can be calculated as follows: TJ(MAX) = TA(MAX) + (JA|Air Flow = 0*P(MAX)). For more information, see "Thermal Characteristic's of Atmel Packages"
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DC Characteristics(1)
Symbol II IOZ ICC1 Parameter Input Leakage Current Tri-State Output Off-State Current Power Supply Current, Standby Condition VIN = VCCINT or Ground VO = VCCINT or GND VCCINT = Max VIN = 0, VCCINT Std Mode Com. Ind. "ITD" Mode ICC2 ICC3(2) VIL VIH VOL Power Supply Current, Power-down Mode Reduced-power Mode Supply Current, Standby Input Low Voltage Input High Voltage 3.3V Output Low Voltage (TTL) VCCIO = 3.0V, IOL = 8 mA VCCIO = 3.0V, IOL = 0.1 mA IOL = 100 A, VCCIO = 2.3V IOL = 1 mA, VCCIO = 2.3V IOL = 2 mA, VCCIO = 2.3V VOH Output High Voltage -3.3V (TTL) Output High Voltage -3.3V (CMOS) 2.5V High Voltage VCCIO = 3.0V, IOH = -2.0 mA VIN = VIH or VIL VCCIO = 3.0V, IOH = -0.1 mA IOH = -100 A, VCCIO = 2.3V IOH = -1 mA, VCCIO = 2.3V Notes: 2.4 VCCIO -0.2 2.1 2.0 Com. Ind. 3.3V Output Low Voltage (CMOS) Com. Ind. 2.5V Low Voltage VCCINT = Max VIN = 0, VCCINT VCCINT = Max VIN = 0, VCCINT Com. Ind. Min -10 -10 Note 3 Note 3 1 1 0.1 Note 3 Note 3 -0.5 1.7 0.8 5.75 0.45 0.45 0.2 0.2 .2 .4 .7 1 Typ Min 10 10 Unit A A mA mA mA mA mA mA mA V V V V V V V V V V V V V V
PD Mode Std Mode Com. Ind.
IOH = -2 mA, VCCIO = 2.3V 1.7 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON. 3. See Characterization Curves for each device.
Power-down AC Characteristics(1)
-4, -5 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV Parameter Valid 1, I/O before PD High Valid 1, OE
(2)
-7 Min 7.5 7.5 7.5 Max Min 10 10 10 15 15 15 1.0
-10 Max Min 12 12 12 20 20 20 1.0
-12 Max Min 15 15 15 22 22 22 1.0
-15 Max Unit ns ns ns 25 25 25 1.0 ns ns ns s
Min 4.5 4.5 4.5
Max
before PD High
(2)
Valid 1, Clock
(2)
before PD High
I, I/O Don't Care after PD High OE Don't Care after PD High
(2)
9.0 9.0 9.0 1.0
Clock
Don't Care after PD High
PD Low to Valid I, I/O
17
2398E-12/01
Power-down AC Characteristics(1)
-4, -5 Symbol tDLGV tDLCV Parameter PD Low to Valid OE, (Pin or Term) PD Low to Valid Clock, (Pin or Term) Min Max 1.0 1.0 1.0 Min -7 Max 1.0 1.0 1.0 Min -10 Max 1.0 1.0 1.0 Min -12 Max 1.0 1.0 1.0 Min -15 Max 1.0 1.0 1.0 Unit s s s
tDLOV PD Low to Valid Output Notes: 1. For slow slew outputs, add tSSO. 2. Pin or product term.
AC Characteristics ATF1502AE(L)(1)
AE -4 Symbol tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT(3) tACNT fACNT fMAX
(4) (5)
AE -7 Min Max 7.5 7.5 4.7 0.0 3.0 0.0
AE -10 Min Max 10 10 6.3 0.0 3.0 0.0
AEL-15(6) Min Max 15 12 11 0.0 3.0 1.0 Unit ns ns ns ns ns MHz 8.0 ns ns ns ns ns 15 ns ns ns 13 77 ns MHz 13 77 77 ns MHz MHz 2.0 2.0 2.0 8.0 1.0 6.0 3.5 3.0 ns ns ns ns ns ns ns ns
Parameter Input or Feedback to Non-registered Output I/O Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay
Min
Max 4.5 4.5
2.9 0.0 2.5 0.0 1.0 2.0 2.0 1.6 0.3 1.0 2.0 2.0 4.4 225 4.4 225 230 0.7 0.7 2.3 1.9 0.5 1.5 0.6 0.0 4.3 3.0
1.0 3.0 3.0 2.5 0.5 1.0 3.0 3.0
5.0
1.0 4.0 4.0 3.6 0.5
6.7
1.0 5.0 5.0 4.0 4.0
7.2
1.0 4.0 4.1
9.4
1.0 6.0 6.0
7.2 133 7.2 133 140 1.2 1.2 2.8 3.1 0.8 2.5 1.0 0.0 100 100 100
9.7
9.7
tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE
1.5 1.5 3.4 4.0 1.0 3.3 1.2 00
18
ATF1502AE(L)
2398E-12/01
ATF1502AE(L)
AC Characteristics ATF1502AE(L)(1) (Continued)
AE -4 Symbol tOD1 tOD2 Parameter Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Disable Delay (CL= 5pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay 1.3 0.6 1.0 1.5 0.7 0.6 1.2 0.6 0.8 1.2 1.2 0.9 Min Max 0.8 1.3 AE -7 Min Max 1.3 1.8 AE -10 Min Max 1.8 2.3 AEL-15(6) Min Max 3.0 3.0 Unit ns ns
tOD3
5.8
6.3
6.8
5.0
ns
tZX1 tZX2
4.0 4.5
4.0 4.5
5.0 5.5
7.0 7.0
ns ns
tZX3
9.0
9.0
10.0
10
ns
tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tRPA Notes:
(2)
4.0 2.0 1.0 1.5 1.5
4.0 2.8 1.3 1.5 1.5 1.2 1.0 2.0 1.0 1.3 1.9 1.9 1.5
5.0 4.0 4.0 2.0 2.0 1.5 1.3 2.5 1.2 1.9 2.6 2.6 2.1
6.0
ns ns ns ns ns
2.0 2.0 7.0 7.0 1.0 5.0 5.0 2.0
ns ns ns ns ns ns ns ns
Reduced Power Adder 2.5 4.0 5.0 14 ns 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipeline data. 6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical, the device will achieve the speeds of the -10 column. (See "ITD/automatic power down.")
19
2398E-12/01
STAND-BY ICC VS. SUPPLY VOLTAGE (TA = 25C)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 4.8
NORMALIZED Icc 1.4 1.2 1.0
NORMALIZED ICC VS. TEMP
ICC (A)
TBD
TBD 0.8 0.6 0.4 -40.0
5.0 SUPPLY VOLTAGE (V)
5.3
5.5
0.0
25.0
75.0
TEMPERATURE (C)
SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
140.000 120.000
1.000 0.800 ICC (mA) 0.600 0.400 0.200 0.000 0.0
SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
100.000 ICC (mA) 80.000 TBD 60.000 40.000 20.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 FREQUENCY (MHz) 25.0 37.5 50.0
TBD
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0 -10 IOH (mA) -20 -30 -40 -50 4.0
OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V)
0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0
OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25C)
IOH (mA)
TBD
TBD
4.5
5.0 SUPPLY VOLTAGE (V)
5.5
6.0
0.00
0.50
1.00
1.50
2.00
2.50 VOH (V)
3.00
3.50
4.00
4.50
5.00
48 46 Iol (mA) 44 42 40 38 36 4.0
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (V OL = 0.5V)
140.0 120.0
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25C)
IOL (mA)
TBD
100.0 80.0 60.0 40.0
TBD
4.5
5.0 SUPPLY VOLTAGE (V)
5.5
6.0
20.0 0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
20
ATF1502AE(L)
2398E-12/01
ATF1502AE(L)
INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, TA = 35C)
40 INPUT CURRENT (uA) 30 20 10 0 -10 -20 -30 0.0 1.0 2.0 3.0 4.0 5.0 6.0 INPUT VOLTAGE (V) TBD
0 INPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 0.0
INPUT CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, T A = 25C)
TBD
-0.2
-0.4 -0.6 INPUT VOLTAGE (V)
-0.8
-1.0
NORMALIZED TPD VS. VCC
1.2 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD
NORMALIZED TPD VS. TEMP
1.1
NORMALIZED TPD
1.0 TBD 0.9
0.8 -40.0
0.0 25.0 TEMPERATURE (C)
75.0
1.3
NORMALIZED TCO
NORMALIZED TCO VS. VCC
1.1 NORMALIZED TCO
NORMALIZED TCO VS. TEMP
1.2 1.1 TBD 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5
1.0 TBD 0.9
0.8 -40.0
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED T SU VS. VCC
1.2 NORMALIZED TSU 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD
NORMALIZED TSU VS. TEMP
1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 -40.0 TBD
0.0
25.0
75.0
TEMPERATURE (C)
21
2398E-12/01
8
DELTA TPD VS. OUTPUT LOADING
8.00 7.00
DELTA TCO VS. OUTPUT LOADING
DELTA TPD (ns)
6 4
DELTA TCO (ns)
6.00 5.00 4.00 3.00 2.00 1.00
TBD
2 0 -2
TBD
0.00
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
0.0
DELTA TPD (ns)
DELTA TPD VS. # OF OUTPUT SWITCHING
DELTA TCO (ns)
0.0
-0.1 -0.2 TBD -0.3 -0.4 -0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING
-0.1 TBD -0.2
-0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING
22
ATF1502AE(L)
2398E-12/01
ATF1502AE(L)
ATF1502AE(L) Pinouts
44-lead PLCC
I/O I/O I/O VCC GCK2/OE2/I GCLR/I OE1/I GCK1/I GND I/O/GCLK3 I/O 44 43 42 41 40 39 38 37 36 35 34 I/O I/O I/O VCC I/OE2/GCK2 GCLR/I I/OE1 GCK1/I GND GCK3 I/O I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 18 19 20 21 22 23 24 25 26 27 28 TDI/I/O I/O I/O GND PD1/I/O I/O I/O/TMS I/O VCC I/O I/O 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40
ATF1502AE(L) ATF1504AE(L)
39 38 37 36 35 34 33 32 31 30 29
I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O
44-lead TQFP
I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O
1 2 3 4 5 6 7 8 9 10 11
ATF1502AE(L) ATF1504AE(L)
33 32 31 30 29 28 27 26 25 24 23
I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O
I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O
12 13 14 15 16 17 18 19 20 21 22
23
2398E-12/01
ATF1502AE(L) Dedicated Pinouts
Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O/GCLK3 I/O/PD (1,2) I/O/TDI (JTAG) I/O/TMS (JTAG) I/O/TCK (JTAG) I/O/TDO (JTAG) GNDINT GNDIO VCCINT VCCIO # of Signal Pins # User I/O Pins 44-lead J-lead 2 1 44 43 41 11, 25 7 13 32 38 22, 42 10, 30 3, 23 15, 35 36 32 44-lead TQFP 40 39 38 37 35 5, 19 1 7 26 32 16, 36 4, 24 17, 41 9, 29 36 32
OE (1, 2) Global OE pins GCLR Global Clear pin GCLK (1, 2, 3) Global Clock pins PD (1, 2) Power-down pins TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming GNDINT Ground pins for the internal device logic GNDIO Ground pins for the I/O drivers VCCINT VCC pins for the internal device logic (+3.3V) VCCIO VCC for the I/O drivers
24
ATF1502AE(L)
2398E-12/01
ATF1502AE(L)
ATF1502AE(L) I/O Pinouts
MC 1 2 3 4/TDI 5 6 7/PD1 8 9/TMS 10 11 12 13 14 15 16 17 18 19 20/TDO 21 22 23 24 25/TCK 26 27 28 29 30 31/PD2 32 PLC A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 44-lead PLCC 4 5 6 7 8 9 11 12 13 14 16 17 18 19 20 21 41 40 39 38 37 36 34 33 32 31 29 28 27 26 25 24 44-lead TQFP 42 43 44 1 2 3 5 6 7 8 10 11 12 13 14 15 35 34 33 32 31 30 28 27 26 25 23 22 21 20 19 18
25
2398E-12/01
ATF1502AE(L) Ordering Information
tPD (ns) 4.5 7.5 tCO1 (ns) 3.0 5.0 FMAX (MHz) 230 140 Ordering Code ATF1502AE-4 AC44 ATF1502AE-4 JC44 ATF1502AE-7 AC44 ATF1502AE-7 JC44 ATF1502AE-7 AI44 ATF1502AE-7 JI44 10.0 6.7 100 ATF1502AE-10 AC44 ATF1502AE-10 JC44 ATF1502AE-10 AI44 ATF1502AE-10 JI44 15.0 8.0 77 ATF1502AEL-15 AC44 ATF1502AEL-15 JC44 Package 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to +85C) Commercial (0C to 70C) Industrial (-40C to +85C) Commercial (0C to 70C)
Using "C" Product for Industrial
There is very little risk in using "C" devices for industrial applications because the VCC conditions for 3.3V products are the same for commercial and industrial (there is only 15C difference at the high end of the temperature range). To use commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type 44A 44J 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC)
26
ATF1502AE(L)
2398E-12/01
ATF1504AE(L)
AC Characteristics ATF1504AE(L) (1)
AE -4 Symbol tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT(3) tACNT fACNT
(4)
AE -7 Min Max 7.5 7.5 4.7 0.0 3.0 0.0
AE -10 Min Max 10 10 6.2 0.0 3.0 0.0
AEL -15(6) Min Max 15 12 11 0.0 3.0 1.0 Unit ns ns ns ns ns MHz 9.0 ns ns ns ns ns 15 ns ns ns 13 77 ns MHz 13 77 77 ns MHz MHz 2.0 2.0 2.0 8.0 1.0 6.0 3.5 3.0 3.0 3.0 5.0 ns ns ns ns ns ns ns ns ns ns ns
Parameter Input or Feedback to Non-registered Output I/O Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
Min
Max 4.5 4.5
2.8 0.0 2.5 0.0 1.0 2.0 2.0 1.6 0.3 1.0 2.0 2.0 4.5 225 4.5 225 230 0.6 0.6 2.5 1.8 0.4 1.5 0.6 0.0 0.8 1.3 5.8 4.3 3.1
1.0 3.0 3.0 2.6 0.4 1.0 3.0 3.0
5.1
1.0 4.0 4.0 3.6 0.6
7.0
1.0 5.0 5.0 5.0 4.0
7.2
1.0 4.0 4.0
9.6
1.0 6.0 6.0
7.4 133 7.4 133 140 1.1 1.1 3.0 3.0 0.7 2.5 1.0 0.0 1.3 1.8 6.3 100 100 100
10
10
fMAX(5) tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3
1.4 1.4 3.7 3.9 0.9 3.2 1.2 00 1.8 2.3 6.8
tZX1
4.0
4.0
5.0
7.0
ns
27
2398E-12/01
AC Characteristics ATF1504AE(L) (Continued)(1)
AE -4 Symbol tZX2 tZX3 Parameter Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Disable Delay (CL= 5pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay 1.3 0.6 1.0 1.5 0.7 0.6 1.2 0.6 1.0 1.3 1.3 1.0 Min Max 4.5 9.0 AE -7 Min Max 4.5 9.0 AE -10 Min Max 5.5 10.0 AEL -15(6) Min Max 7.0 10 Unit ns ns
tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tRPA Notes:
(2)
4.0 2.0 1.0 1.5 1.5
4.0 2.9 1.3 1.5 1.5 1.2 0.9 1.9 1.0 1.5 2.1 2.1 1.7
5.0 5.0 4.0 2.0 2.0 1.6 1.3 2.5 1.2 2.2 2.9 2.9 2.3
6.0
ns ns ns ns ns
2.0 2.0 6.0 6.0 2.0 4.0 4.0 2.0
ns ns ns ns ns ns ns ns
Reduced Power Adder 3.5 4.0 5.0 10 ns 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipeline data. 6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical, the device will achieve the speeds of the -10 column. (See "ITD/automatic power down.")
28
ATF1504AE(L)
2398E-12/01
ATF1504AE(L)
NORMALIZED ICC VS. TEMP
1.4 NORMALIZED Icc 1.2 1.0 TBD 0.8 0.6 0.4 -40.0
STAND-BY ICC VS. SUPPLY VOLTAGE (TA = 25C)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 4.8
ICC (A)
TBD
5.0 SUPPLY VOLTAGE (V)
5.3
5.5
0.0
25.0
75.0
TEMPERATURE (C)
SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
140.000
ICC (mA)
1.000 0.800
SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
120.000 100.000 ICC (mA) 80.000 TBD 60.000 40.000 20.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 FREQUENCY (MHz) 25.0 37.5 50.0
0.600 0.400 0.200 0.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 FREQUENCY (MHz) TBD
0 -10 IOH (mA)
OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V)
0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0
OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25C)
-30 -40 -50 4.0 4.5
TBD
IOH (mA)
-20
TBD
5.0 SUPPLY VOLTAGE (V)
5.5
6.0
0.00
0.50
1.00
1.50
2.00
2.50 VOH (V)
3.00
3.50
4.00
4.50
5.00
48 46 Iol (mA) 44 42 40 38 36 4.0
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (V OL = 0.5V)
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25C)
140.0 120.0 100.0
TBD
IOL (mA)
80.0 60.0 40.0
TBD
4.5
5.0 SUPPLY VOLTAGE (V)
5.5
6.0
20.0 0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
29
2398E-12/01
0 INPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 0.0
INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, TA = 35C)
INPUT CURRENT (uA)
40 30 20 10 0 -10 -20 -30 0.0
INPUT CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, T A = 25C)
TBD
TBD
-0.2
-0.4 -0.6 INPUT VOLTAGE (V)
-0.8
-1.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
1.2 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD NORMALIZED TPD 1.1
NORMALIZED TPD VS. TEMP
1.0 TBD 0.9
0.8 -40.0
0.0 25.0 TEMPERATURE (C)
75.0
1.3 NORMALIZED TCO 1.2 1.1
NORMALIZED TCO VS. VCC
1.1 NORMALIZED TCO
NORMALIZED TCO VS. TEMP
1.0 TBD 0.9
TBD 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5
0.8 -40.0
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED T SU VS. VCC
1.2 NORMALIZED TSU 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD
NORMALIZED TSU VS. TEMP
1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 -40.0 TBD
0.0
25.0
75.0
TEMPERATURE (C)
30
ATF1504AE(L)
2398E-12/01
ATF1504AE(L)
8
DELTA TPD VS. OUTPUT LOADING
8.00 7.00
DELTA TCO VS. OUTPUT LOADING
DELTA TPD (ns)
6 4
DELTA TCO (ns)
6.00 5.00 4.00 3.00 2.00 1.00
TBD
2 0 -2
TBD
0.00
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
0.0
DELTA TPD (ns)
DELTA TPD VS. # OF OUTPUT SWITCHING
DELTA TCO (ns)
0.0
-0.1 -0.2 TBD -0.3 -0.4 -0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING
-0.1 TBD -0.2
-0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING
31
2398E-12/01
ATF1504AE(L) Pinouts
44-lead PLCC - Top View
I/O I/O I/O VCC GCK2/OE2/I GCLR/I OE1/I GCK1/I GND I/O/GCLK3 I/O
44-lead TQFP - Top View
I/O I/O I/O VCC I/OE2/GCK2 GCLR/I I/OE1 GCK1/I GND GCK3 I/O I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
18 19 20 21 22 23 24 25 26 27 28
TDI/I/O I/O I/O GND PD1/I/O I/O I/O/TMS I/O VCC I/O I/O
7 8 9 10 11 12 13 14 15 16 17
6 5 4 3 2 1 44 43 42 41 40
ATF1502AE(L) ATF1504AE(L)
39 38 37 36 35 34 33 32 31 30 29
I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O
1 2 3 4 5 6 7 8 9 10 11
ATF1502AE(L) ATF1504AE(L)
I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O
I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O
100-lead TQFP
I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
ATF1504AE(L) ATF1508AE(L) ATF1516AE(L)
32
ATF1504AE(L)
2398E-12/01
GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O I/O I/O
26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O
I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO
12 13 14 15 16 17 18 19 20 21 22
ATF1504AE(L)
ATF1504AE(L) 49-ball 0.8 mm Pitch Bottom View
A B C D E F G 7 6 5 4 3 2 1
ATF1504AE(L) ATF1508AE(L) ATF1516AE(L) 100-ball 1.0 mm Pitch Bottom View
A B C D E F G H J K 10 9 8 7 6 5 4 3 2 1
33
2398E-12/01
ATF1504AE(L) Dedicated Pinouts
Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O /GCLK3 I/O/PD (1,2) I/O/TDI (JTAG) I/O/TMS (JTAG) I/O/TCK (JTAG) I/O/TDO (JTAG) GNDINT GNDIO VCCINT VCCIO N/C 44-lead TQFP 40 39 38 37 35 5, 19 1 7 26 32 16, 36 4, 24 17, 41 9, 29 44-lead J-lead 2 1 44 43 41 11, 25 7 13 32 38 22, 44 10, 30 3, 23 15, 35 49-ball BGA B4 A3 A4 A5 C4 D1, G5 B1 F1 F7 B7 C2, E6 B5, F4 B3, E4 C6, E2 100-ball BGA A5 B5 B6 A6 C6 E1, H6 A1 F3 F8 A10 C3, D6, D7, E5, F6, G4, G5, H8 - D5, G6 C8, D4, E6, F5, G7, H3 B1, B10, C1, C9, C10, D8, E3, E4, H1, H9, H10, J1, J2, J10, K1, K9 68 64 100-lead TQFP 90 89 88 87 85 12, 42 4 15 62 73 38, 86 11, 26, 43, 59, 74, 95 39, 91 3, 18, 34, 51, 66, 82 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 68 64
# of Signal Pins # User I/O Pins
36 32
36 32
41 37
OE (1, 2) Global OE pins GCLR Global Clear pin GCLK (1, 2, 3) Global Clock pins PD (1, 2) Power-down pins TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming GNDINT Ground pins for the internal device logic GNDIO Ground pins for the I/O pins VCCINT VCC pins for the internal device logic VCCIO VCC for the I/O drivers
34
ATF1504AE(L)
2398E-12/01
ATF1504AE(L)
ATF1504AE(L) I/O Pinouts
MC 1 2 3 4 5 6 7 8/ TDI 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32/ TMS PLC A A A/ PD1 A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 44-lead 44-lead 49-ball 84-lead PLCC TQFP BGA PLCC 12 11 9 8 7 6 5 4 21 20 19 18 17 16 14 13 6 5 3 2 1 44 43 42 15 14 13 12 11 10 8 7 D2 D1 D4 C1 B1 B2 A1 A2 C3 G4 E3 G3 F3 G2 G1 F2 D3 E1 F1 22 21 20 18 17 16 15 14 12 11 10 9 8 6 5 4 41 40 39 37 36 35 34 33 31 30 29 28 27 25 24 23 100ball BGA F4 E2 E1 D2 D1 D3 C2 A1 B2 A2 A3 B3 A4 B4 C4 C5 K5 J5 H5 K4 J4 H4 J3 K3 K2 H2 G2 G1 G3 F2 F1 F3 100lead TQFP 14 13 12 10 9 8 6 4 100 99 98 97 96 94 93 92 37 36 35 33 32 31 30 29 25 23 21 20 19 17 16 15 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48/ TCK 49 50 51 52 53 54 55 56/ TDO 57 58 59 60 61 62 63 64 PLC C C C/ PD2 C C C C C C C C C C C C C D D D D D D D D D D D D D D D D/ GCLK3 44-lead 44-lead 49-ball 84-lead PLCC TQFP BGA PLCC 24 25 26 27 28 29 31 32 33 34 36 37 38 39 40 41 18 19 20 21 22 23 25 26 27 28 30 31 32 33 34 35 E5 G5 F5 G6 G7 F6 D5 E7 F7 D7 D6 C7 B6 B7 A7 A6 C5 C4 44 45 46 48 49 50 51 52 54 55 56 57 58 60 61 62 63 64 65 67 68 69 70 71 73 74 75 76 77 79 80 81 100ball BGA K6 J6 H6 K7 J7 H7 J8 K8 K10 J9 G9 G10 G8 F9 F10 F8 F7 E9 E10 E8 E7 D9 D10 A10 B9 A9 A8 B8 A7 B7 C7 C6 100lead TQFP 40 41 42 44 45 46 47 48 52 54 56 57 58 60 61 62 63 64 65 67 68 69 71 73 75 76 79 80 81 83 84 85
35
2398E-12/01
ATF1504AE(L) Ordering Information
tPD (ns) 4.5 tCO1 (ns) 3.1 fMAX (MHz) 225 Ordering Code ATF1504AE-4 AC44 ATF1504AE-4 JC44 ATF1504AE-4 CC49 ATF1504AE-4 AC100 ATF1504AE-4 CTC100 ATF1504AE-7 AC44 ATF1504AE-7 JC44 ATF1504AE-7 CC49 ATF1504AE-7 AC100 ATF1504AE-7 CTC100 ATF1504AE-7 AI44 ATF1504AE-7 JI44 ATF1504AE-7 CI49 ATF1504AE-7 AI100 ATF1504AE-7 CTI100 10.0 7.0 100 ATF1504AE-10 AC44 ATF1504AE-10 JC44 ATF1504AE-10 CC49 ATF1504AE-10 AC100 ATF1504AE-10 CTC100 ATF1504AE-10 AI44 ATF1504AE-10 JI44 ATF1504AE-10 CI49 ATF1504AE-10 AI100 ATF1504AE-10 CTI100 15.0 9.0 77 ATF1504AEL-15 AC44 ATF1504AEL-15 JC44 ATF1504AEL-15 CC49 ATF1504AEL-15 AC100 ATF1504AEL-15CTC100 Package 44A 44J 49C1 100A 100CT1 44A 44J 49C1 100A 100CT1 44A 44J 49C1 100A 100CT1 44A 44J 49C1 100A 100CT1 44A 44J 49C1 100A 100CT1 44A 44J 49C1 100A 100CT1 Operation Range Commercial (0C to 70C)
7.5
5.1
133
Commercial (0C to 70C)
Industrial (-40C to +85C)
Commercial (0C to 70C)
Industrial (-40C to +85C)
Commercial (0C to 70C)
Using "C" Product for Industrial
There is very little risk in using "C" devices for industrial applications because the VCC conditions for 3.3V products are the same for commercial and industrial (there is only 15C difference at the high end of the temperature range). To use commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type 44A 44J 49C1 100A 100CT1 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC) 49-lead, Chip Scale Ball Grid Array (CBGA) 0.8 mm pitch 100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP) 100-lead, Tape Ball Grid Array (TBGA) 1.0 mm pitch
36
ATF1504AE(L)
2398E-12/01
ATF1508AE(L)
AC Characteristics ATF1508AE(L) (1)
AE -5 Symbol tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT(3) tACNT fACNT
(4)
AE -7 Min Max 7.5 7.5 4.9 0 3 0
AE -10 Min Max 10 10 6.6 0 3 0 5 1 4 4 3.8 0.3 6.6
AEL -15(6) Min 3 3 11 0 3 1 9 5 5 5 4 Max Unit ns ns ns ns ns MHz ns ns ns ns ns 15 6 6 ns ns ns 13 77 ns MHz 13 77 77 ns MHz MHz 2 2 2 8 1 6 3.5 3 3 3 5 ns ns ns ns ns ns ns ns ns ns ns
Parameter Input or Feedback to Non-registered Output I/O Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
Min
Max 5 5
3.3 0 2.5 0 1 2 2 1.8 0.2 1 2 2 5.2 193 5.2 193 200 0.7 0.7 2.5 2 0.4 1.6 0.7 0 0.8 1.3 5.8 4.9 3.4
1 3 3 2.8 0.3 1 3 3
7.1
1 4 4
9.4
7.7 130 7.7 130 133 1 1 3 2.9 0.7 2.4 1 0 1.2 1.7 6.2 100 100 100
10.2
10.2
fMAX(5) tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3
1.4 1.4 3.4 3.8 0.9 3.1 1.3 0 1.6 2.1 6.6
tZX1
4
4
5
7
ns
37
2398E-12/01
AC Characteristics ATF1508AE(L) (Continued)(1)
AE -5 Symbol tZX2 tZX3 Parameter Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Disable Delay (CL= 5pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay 1.4 0.6 1.1 1.4 0.8 0.5 1.2 0.7 1.1 1.4 1.4 1.4 Min Max 4.5 9 AE -7 Min Max 4.5 9 AE -10 Min Max 5.5 10 AEL -15(6) Min Max 7 10 Unit ns ns
tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tRPA Notes:
(2)
4 2.1 1 1.6 1.4
4 2.9 1.3 1.6 1.4 1.2 0.9 1.7 1 1.6 2 2 2
5 5 4 2 2 1.6 1.3 2.2 1.3 2 2.7 2.7 2.6
6
ns ns ns ns ns
2 2 6 6 2 4 4 2
ns ns ns ns ns ns ns ns
Reduced Power Adder 4.0 4.0 5 10 ns 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipeline data. 6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical, the device will achieve the speeds of the -10 column. (See "ITD/automatic power down.")
38
ATF1508AE(L)
2398E-12/01
ATF1508AE(L)
STAND-BY ICC VS. SUPPLY VOLTAGE (TA = 25C)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 4.8
NORMALIZED Icc 1.4 1.2 1.0 TBD 0.8 0.6 0.4 -40.0
NORMALIZED ICC VS. TEMP
ICC (A)
TBD
5.0 SUPPLY VOLTAGE (V)
5.3
5.5
0.0
25.0
75.0
TEMPERATURE (C)
SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
140.000 120.000
1.000 0.800 ICC (mA) 0.600 0.400 0.200 0.000 0.0
SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
100.000 ICC (mA) 80.000 TBD 60.000 40.000 20.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 FREQUENCY (MHz) 25.0 37.5 50.0
TBD
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0 -10 IOH (mA) -20 -30 -40 -50 4.0
OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V)
0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0
OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25C)
IOH (mA)
TBD
TBD
4.5
5.0 SUPPLY VOLTAGE (V)
5.5
6.0
0.00
0.50
1.00
1.50
2.00
2.50 VOH (V)
3.00
3.50
4.00
4.50
5.00
48 46 Iol (mA) 44 42 40 38 36 4.0
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (V OL = 0.5V)
140.0 120.0
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25C)
IOL (mA)
TBD
100.0 80.0 60.0 40.0
TBD
4.5
5.0 SUPPLY VOLTAGE (V)
5.5
6.0
20.0 0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
39
2398E-12/01
0 INPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 0.0
INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, T A = 35C)
INPUT CURRENT (uA)
40 30 20 10 0 -10 -20 -30 0.0
INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5.0V, TA = 25C)
TBD
TBD
-0.2
-0.4 -0.6 INPUT VOLTAGE (V)
-0.8
-1.0
1.0
2.0 3.0 4.0 INPUT VOLTAGE (V)
5.0
6.0
NORMALIZED TPD VS. VCC
1.2 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD NORMALIZED TPD 1.1
NORMALIZED T PD VS. TEMP
1.0 TBD 0.9
0.8 -40.0
0.0 25.0 TEMPERATURE (C)
75.0
1.3 NORMALIZED TCO 1.2 1.1
NORMALIZED TCO VS. VCC
1.1 NORMALIZED TCO
NORMALIZED T CO VS. TEMP
1.0 TBD 0.9
TBD 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5
0.8 -40.0
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
1.2 NORMALIZED TSU 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD
NORMALIZED TSU VS. TEMP
1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 -40.0 TBD
0.0
25.0
75.0
TEMPERATURE (C)
40
ATF1508AE(L)
2398E-12/01
ATF1508AE(L)
8
DELTA TPD VS. OUTPUT LOADING
8.00 7.00
DELTA TCO VS. OUTPUT LOADING
DELTA TPD (ns)
6 4
DELTA TCO (ns)
6.00 5.00 4.00 3.00 2.00 1.00
TBD
2 0 -2
TBD
0.00
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
0.0
DELTA TPD (ns)
DELTA TPD VS. # OF OUTPUT SWITCHING
DELTA TCO (ns)
0.0
-0.1 -0.2 TBD -0.3 -0.4 -0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING
-0.1 TBD -0.2
-0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING
41
2398E-12/01
ATF1508AE(L) Pinouts
84-lead PLCC - Top View
I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O
100-lead TQFP - Top View
I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O
I/O I/O GND I/O/TDO I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O VCCIO
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O/PD1 VCCIO I/O/TDI I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O GND
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ATF1508AE(L)
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
ATF1504AE(L) ATF1508AE(L) ATF1516AE(L)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO
144-lead TQFP - Top View
144 127 1 108
19
ATF1508AE(L) ATF1516AE(L) ATF1532AE(L)
36 54 72
42
ATF1508AE(L)
2398E-12/01
GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O I/O I/O
26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
90
ATF1508AE(L)
ATF1504AE(L) ATF1508AE(L) ATF1516AE(L) 100-ball 1.0 mm Pitch Bottom View
A B C D E F G H J K 10 9 8 7 6 5 4 3 2 1
ATF1508AE(L) 169-ball 0.8 mm Pitch Bottom View
A B C D E F G H J K L M N 13 12 11 10 9 8 7 6 5 4 3 2 1
43
2398E-12/01
ATF1508AE(L) ATF1516AE(L) ATF1532AE(L) 256-ball 1.0 mm Pitch Bottom View
A B C D E F G H J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
44
ATF1508AE(L)
2398E-12/01
ATF1508AE(L)
ATF1508AE(L) Dedicated Pinouts
Dedicated Pin INPUT/GCLK1 INPUT/GCLR INPUT/OE1 INPUT/OE2/GCK2 I/O/GCLK3 I/O PD (1,2) TDI (JTAG) TMS (JTAG) TCK (JTAG) TDO (JTAG) GNDINT GNDIO 84-pin J-Lead 83 1 84 2 81 12, 45 14 23 62 71 42, 82 7, 19, 32, 47, 59, 72 3, 43 13, 26, 38, 53, 66, 78 100-pin TQFP 87 89 88 90 85 1,41 4 15 62 73 38,86 11, 26, 43, 59, 74, 95 39, 91 3, 18, 34, 51, 66, 82 100-ball BGA A6 B5 B6 A5 C6 B1, J6 A1 F3 F8 A10 D6, G5 C3, D7, E5, F6, G4, H8 D5, G6 C8, D4, E6, F5, G7, H3 144-pin TQFP 125 127 126 128 119 142, 61 4 20 89 104 52, 57, 124, 129 3, 13, 17, 33, 59, 64, 85, 105, 135 51, 58, 123, 130 24, 50, 73, 76, 95, 115, 144 1, 2, 12, 19, 34, 35, 36, 43, 46, 47, 48, 49, 66, 75, 90, 103, 108, 120, 121, 122 169-ball BGA D8 D6 D7 E7 A8 D4, H8 E4 J4 J10 E10 A7, E8, J7, N7 A3, A12, E1, F5, F13, H1, H9, J13, N2, N11 B7, E6, H7, M7 A2, A11, E13, F1, F9, H5, H13, J1, N3, N12 B5, B6, B8, B9, C5, C6, C7, C8, C9, C10, E2, E3, E11, E12, F2, F3, F11, F12, G1, G3, G11, G12, H2, H3, H11, H12, J2, J3, J11, J12, L4, L5, L6, L7, L8, L9, M5, M6, M8, M9 256-ball BGA D9 E8 E9 D8 F9 E4, M9 D4 J6 J11 D13 A8, C9, G9, K8, P9 A3, B10, C2, D14, F6, G10, H8, J9, K7, L11, M3, P6, P10, R2, R3, T1, T15 B9, C8, G8, K9, P8 B3, B5, C14, E15, F11, G3, G7, G15, H9, J8, K10, L3, L6, M15, P14, T2, T3 A1, A2, A4, A5, A6, A7, A9, A10, A11, A12, A13, A14, A15, A16, B1, B2, B4, B6, B7, B8, B11, B12, B13, B14, B15, B16, C1, C3, C4, C6, C11, C13, C15, C16, D1, D2, D3, D15, D16, E1, E2, E3, E14, E16, F1, F2, F15, F16, G1, G2, G14, G16, H1, H2, H15, H16, J1, J2, J15, J16, K1, K2, K3, K14, K15, K16, L1, L2, L15, L16, M1, M14, M16, N1, N2, N3, N14, N15, N16, P1, P2, P3, P4, P12, P13, P15, P16, R1, R4, R5, R6, R7, R8, R9, R11, R12, R13, R14, R15, R16, T4, T5, T6, T8, T9, T10, T11, T12, T13, T14, T16 100 96
VCCINT VCCIO
No Connect
# of Signal pins # of User I/O pins
68 64
84 80
84 80
100 96
100 96
OE (1,2) Global OE pins. GCLR Global Clear pin. GCLK (1,2,3) Global Clock pins. TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing. GNDINT Ground pins for the internal device logic. GNDIO Ground pins for the I/O drivers. VCCINT VCC pins for the internal device logic. VCCIO VCC pins for the I/O drivers.
45
2398E-12/01
ATF1508AE(L) I/O Pinouts
MC 1 2 3/PD1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32/ TDI PLB A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 84-pin J-Lead 12 11 10 9 8 6 5 4 22 21 20 18 17 16 15 14 100-pin 100-ball 144-pin 169-ball 256-ball TQFP BGA TQFP BGA BGA 2 1 100 99 98 97 96 94 93 92 14 13 12 10 9 8 7 6 5 4 C1 B1 B2 A2 A3 B3 A4 B4 C4 C5 F4 E2 E1 E3 E4 D2 D1 D3 C2 A1 143 142 141 140 139 138 137 136 134 133 132 131 18 16 15 14 11 10 9 8 7 6 5 4 E5 D4 B2 B3 C3 C4 B4 A4 D5 A5 F6 A6 D1 G5 D2 G4 D3 C1 C2 G7 B1 F4 A1 E4 F4 E4 C5 E5 D5 D6 E6 D7 C7 E7 F7 F8 J7 H5 H3 H4 H6 H7 G5 G4 F3 G6 F5 D4 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48/ TMS 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PLB C C C C C C C C C C C C C C C C D D D D D D D D D D D D D D D D 84-pin J-Lead 31 30 29 28 27 25 24 23 41 40 39 37 36 35 34 33 100-pin 100-ball 144-pin 169-ball 256-ball TQFP BGA TQFP BGA BGA 25 24 23 22 21 20 19 17 16 15 37 36 35 33 32 31 30 29 28 27 K1 J1 H1 H2 G2 G1 G3 F2 F1 F3 K5 J5 H5 K4 J4 H4 J3 K3 J2 K2 32 31 30 29 28 27 26 25 23 22 21 20 56 55 54 53 45 44 42 41 40 39 38 37 K4 J5 N1 M1 L1 L2 K3 G6 K2 H4 K1 J4 N6 K7 N5 H6 N4 K6 M4 J6 M3 L3 M2 K5 N4 M4 M2 L4 L5 K5 K4 K6 J3 J5 J4 J6 N8 M8 P7 L8 N7 M7 L7 M6 P5 N6 M5 N5
46
ATF1508AE(L)
2398E-12/01
ATF1508AE(L)
ATF1508AE(L) I/O Pinouts
MC 65 66 67/ PD2 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96/ TCK PLB E E E E E E E E E E E E E E E E F F F F F F F F F F F F F F F F 84-pin 100-pin 100-ball 144-pin 169-ball 256-ball J-Lead TQFP BGA TQFP BGA BGA 44 45 46 48 49 50 51 52 54 55 56 57 58 60 61 62 40 41 42 44 45 46 47 48 49 50 52 53 54 55 56 57 58 60 61 62 K6 J6 H6 K7 J7 H7 J8 K8 K9 K10 J10 H10 H9 J9 G9 G10 G8 F9 F10 F8 60 61 62 63 65 67 68 69 70 71 72 74 77 78 79 80 81 82 83 84 86 87 88 89 L10 H8 N8 K8 N9 J8 M10 K9 N10 K10 L11 M11 M12 J9 N13 M13 L13 L12 K13 G8 K12 H10 K11 J10 N9 M9 R10 L9 N10 M10 L10 M11 P11 N11 N12 N13 M13 L13 L14 L12 M12 K12 K13 K11 J14 J12 J13 J11 MC 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112/ TDO 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128/ GCLK3 PLB G G G G G G G G G G G G G G G G H H H H H H H H H H H H H H H H 84-pin 100-pin 100-ball 144-pin 169-ball 256-ball J-Lead TQFP BGA TQFP BGA BGA 63 64 65 67 68 69 70 71 73 74 75 76 77 79 80 81 63 64 65 67 68 69 70 71 72 73 75 76 77 78 79 80 81 83 84 85 F7 E9 E10 E8 E7 D9 D10 D8 C9 A10 C10 B10 B9 A9 A8 B8 A7 B7 C7 C6 91 92 93 94 96 97 98 99 100 101 102 104 106 107 109 110 111 112 113 114 116 117 118 119 G13 G10 D13 G9 D12 D11 C13 F10 C12 E9 B13 E10 A13 D10 B12 D9 C11 B11 B10 F8 A10 F7 A9 A8 J10 H12 H14 H13 H11 H10 G12 G13 F14 G11 F12 D13 F13 E13 C12 E12 D12 D11 E11 D10 C10 E10 F10 F9
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2398E-12/01
ATF1508AE(L) Ordering Information
tPD (ns) 5.0 tCO1 (ns) 3.4 fMAX (MHz) 200 Ordering Code ATF1508AE-5 JC84 ATF1508AE-5 AC100 ATF1508AE-5 CTC100 ATF1508AE-5 AAC144 ATF1508AE-5 CC169 ATF1508AE-5 CTC256 ATF1508AE-7 JC84 ATF1508AE-7 AC100 ATF1508AE-7 CTC100 ATF1508AE-7 AAC144 ATF1508AE-7 CC169 ATF1508AE-7 CTC256 ATF1508AE-7 JI84 ATF1508AE-7 AI100 ATF1508AE-7 CTI100 ATF1508AE-7 AAI144 ATF1508AE-7 CI169 ATF1508AE-7 CTI256 10.0 6.6 100 ATF1508AE-10 JC84 ATF1508AE-10 AC100 ATF1508AE-10 CTC100 ATF1508AE-10 AAC144 ATF1508AE-15 CC169 ATF1508AE-10 CTC256 ATF1508AE-10 JI84 ATF1508AE-10 AI100 ATF1508AE-10 CTI100 ATF1508AE-10 AAI144 ATF1508AE-10 CI169 ATF1508AE-10 CTI256 15.0 9.0 77 ATF1508AEL-15 JC84 ATF1508AEL-15 AC100 ATF1508AEL-15 CTC100 ATF1508AEL-15 AAC144 ATF1508AEL-15 CC169 ATF1508AEL-15 CTC256 Package 84J 100A 100CT1 144AA 169C1 256CT1 84J 100A 100CT1 144AA 169C1 256CT1 84J 100A 100CT1 144AA 169C1 256CT1 84J 100A 100CT1 144AA 169C1 256CT1 84J 100A 100CT1 144AA 169C1 256CT1 84J 100A 100CT1 144AA 169C1 256CT1 Operation Range Commercial (0C to 70C)
7.5
5.0
133
Commercial (0C to 70C)
Industrial (-40C to +85C)
Commercial (0C to 70C)
Industrial (-40C to +85C)
Commercial (0C to 70C)
Using "C" Product for Industrial
There is very little risk in using "C" devices for industrial applications because the VCC conditions for 3.3V products are the same for commercial and industrial (there is only 15C difference at the high end of the temperature range). To use commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type 84J 100A 100CT1 144AA 169C1 256CT1 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP) 100-lead, Tape Ball Grid Array (TBGA) 1.0 mm pitch 144-lead, Low Profile Plastic Gull Wing Quad Flatpack (TQFP) 169-lead, Chip Scale Ball Grid Array (CBGA) 0.8 mm pitch 256-lead, Tape Ball Grid Array (TBGA) 1.0 mm pitch
48
ATF1508AE(L)
2398E-12/01
ATF1516AE(L)
AC Characteristics ATF1516AE(L) (1)
AE -5 Symbol tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT(3) tACNT fACNT
(4)
AE -7 Min Max 7.5 7.5 5.2 0 3 0
AE -10 Min Max 10 10 6.9 0 3 0
AEL -15(6) Min Max 15 12 11 0 3 1 Unit ns ns ns ns ns MHz 9 5 5 5 4 ns ns ns ns ns 15 6 6 ns ns ns 13 77 ns MHz 13 77 77 ns MHz MHz 2 2 2 8 1 6 3.5 3 3 3 5 ns ns ns ns ns ns ns ns ns ns ns
Parameter Input or Feedback to Non-registered Output I/O Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF)
Min
Max 5.5 5.5
3.9 0 2.5 0 1 2 2 2.0 0.2 1 2 2 5.8 175 5.8 175 200 0.7 0.7 2.4 2.1 0.3 1.7 0.8 0 0.9 1.4 5.9 5.4 3.5
1 3 3 2.7 0.3 1 3 3
4.8
1 4 4 3.6 0.5
6.4
7.3
1 4 4
9.7
7.9 125 7.9 125 133 0.9 0.9 2.9 2.8 0.5 2.2 1.0 0 1.2 1.7 6.2 100 100 100
10.5
10.5
fMAX(5) tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3
1.2 1.2 3.4 3.7 0.6 2.8 1.3 0 1.6 2.1 6.6
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2398E-12/01
AC Characteristics ATF1516AE(L) (Continued)(1)
AE -5 Symbol tZX1 tZX2 tZX3 Parameter Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Disable Delay (CL= 5pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay 1.5 0.7 1.1 1.4 0.9 0.5 1.2 0.8 1.0 1.6 1.6 1.7 Min Max 4.0 4.5 9 AE -7 Min Max 4.0 4.5 9 AE -10 Min Max 5.0 5.5 10 AEL -15(6) Min Max 7 7 10 Unit ns ns ns
tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM
4 2.1 0.9 1.6 1.4
4 2.9 1.2 1.6 1.4 1.2 0.8 1.6 1.0 1.5 2.3 2.3 2.4
5 5 4 2 2 1.6 1.2 2.1 1.3 2.1 3.0 3.0 3.2 |
6
ns ns ns ns ns
2 2 6 6 2 4 4 2
ns ns ns ns ns ns ns ns
tRPA Reduced Power Adder(2) 4.0 4.0 5.0 10 ns Notes: 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipeline data. 6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical, the device will achieve the speeds of the -10 column. (See "ITD/automatic power down.")
50
ATF1516AE(L)
2398E-12/01
ATF1516AE(L)
NORMALIZED ICC VS. TEMP
1.4 NORMALIZED Icc 1.2 1.0 TBD 0.8 0.6 0.4 -40.0
STAND-BY ICC VS. SUPPLY VOLTAGE (TA = 25C)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 4.8
ICC (A)
TBD
5.0 SUPPLY VOLTAGE (V)
5.3
5.5
0.0
25.0
75.0
TEMPERATURE (C)
SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
140.000
ICC (mA)
1.000 0.800 0.600 0.400 0.200 0.000
SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
120.000 100.000 ICC (mA) 80.000 TBD 60.000 40.000 20.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 FREQUENCY (MHz) 25.0 37.5 50.0
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0 -10 IOH (mA)
OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V)
0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0
OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25C)
-30 -40 -50 4.0 4.5
TBD
IOH (mA)
-20
TBD
5.0 SUPPLY VOLTAGE (V)
5.5
6.0
0.00
0.50
1.00
1.50
2.00
2.50 VOH (V)
3.00
3.50
4.00
4.50
5.00
48 46 Iol (mA) 44 42 40 38 36 4.0
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (V OL = 0.5V)
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25C)
140.0 120.0 100.0
TBD
IOL (mA)
80.0 60.0 40.0
TBD
4.5
5.0 SUPPLY VOLTAGE (V)
5.5
6.0
20.0 0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
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2398E-12/01
0 INPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 0.0
INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, T A = 35C)
INPUT CURRENT (uA)
40 30 20 10 0 -10 -20 -30 0.0
INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5.0V, TA = 25C)
TBD
TBD
-0.2
-0.4 -0.6 INPUT VOLTAGE (V)
-0.8
-1.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
1.2 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD NORMALIZED TPD 1.1
NORMALIZED T PD VS. TEMP
1.0 TBD 0.9
0.8 -40.0
0.0 25.0 TEMPERATURE (C)
75.0
1.3
NORMALIZED TCO
NORMALIZED TCO VS. VCC
1.1 NORMALIZED TCO
NORMALIZED T CO VS. TEMP
1.2 1.1 TBD 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5
1.0 TBD 0.9
0.8 -40.0
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
1.2 NORMALIZED TSU 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD
NORMALIZED TSU VS. TEMP
1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 -40.0 TBD
0.0
25.0
75.0
TEMPERATURE (C)
52
ATF1516AE(L)
2398E-12/01
ATF1516AE(L)
8
DELTA TPD VS. OUTPUT LOADING
8.00 7.00
DELTA TCO VS. OUTPUT LOADING
DELTA TPD (ns)
6 4
DELTA TCO (ns)
6.00 5.00 4.00 3.00 2.00 1.00
TBD
2 0 -2
TBD
0.00
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
0.0
DELTA TPD (ns)
DELTA TPD VS. # OF OUTPUT SWITCHING
DELTA TCO (ns)
0.0
-0.1 -0.2 TBD -0.3 -0.4 -0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
-0.1 TBD -0.2
-0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
NUMBER OF OUTPUTS SWITCHING
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2398E-12/01
ATF1516AE(L) Pinouts
100-lead TQFP - Top View
I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O
144-lead TQFP - Top View
144 127 1 108
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
ATF1504AE(L) ATF1508AE(L) ATF1516AE(L)
I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO
19
ATF1508AE(L) ATF1516AE(L) ATF1532AE(L)
90
GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O I/O I/O
26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
36 54 72
2398E-12/01
208-lead PQFP - Top View
208 183
1
156
26
ATF1516AE(L) ATF1532AE(L)
131
54
ATF1516AE(L)
104
53
78
ATF1516AE(L)
ATF1504AE(L) ATF1508AE(L) ATF1516AE(L) 100-ball 1.0 mm Pitch - Bottom View
A B C D E F G H J K 10 9 8 7 6 5 4 3 2 1
ATF1508AE(L) ATF1516AE(L) ATF1532AE(L) 256-ball 1.0 mm Pitch - Bottom View
A B C D E F G H J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
55
2398E-12/01
ATF1516AE(L) Dedicated Pinouts
Dedicated Pin INPUT/GCLK1 INPUT/GCLR INPUT/OE1 INPUT/OE2/GCK2 I/O/GCLK3 I/O PD (1,2) TDI (JTAG) TMS (JTAG) TCK (JTAG) TDO (JTAG) GNDINT GNDIO 100-pin TQFP 87 89 88 90 TBD TBD 4 15 62 73 38, 86 11, 26, 43, 59, 74, 95 39, 91 3, 18, 34, 51, 66, 82 100-ball BGA A6 B5 B6 A5 TBD TBD A1 F3 F8 A10 D6, G5 C3, D7, E5, F6, G4, H8 D5, G6, C8, D4, E6, F5, G7, H3 144-pin TQFP 125 127 126 128 TBD TBD 4 20 89 104 52, 57, 124, 129 3, 13, 17, 33, 59, 64, 85, 105, 135 51, 58, 123, 130 24, 50, 73, 76, 95, 115, 144 208-pin PQFP 184 182 183 181 TBD TBD 176 127 30 189 75, 82, 180, 185 14, 32, 50, 72, 94, 116, 134, 152, 174, 200 74, 83, 179, 186 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 1,2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 256-ball BGA D9 E8 E9 D8 TBD TBD D4 J6 J11 D13 A8, C9, G9, K8, P9 A3, B10, C2, D14, F6, G10, H8, J9, K7, L11, M3, P6, P10, R2, R3, T1, T15
VCCINT VCCIO
B9, C8, G8, K9, P8 B3, B5, C14, E15, F11, G3, G7, G15, H9, J8, K10, L3, L6, M15, P14, T2, T3 A1, A2, A6, A12, A13, A14, A15, A16, B1, B2, B15, B16, C1, C15, C16, D1, D3, D15, D16, G1, G16, H15, H16, J1, K1, L1, L2, M1, M16, N1, N16, P1, P2, P15, P16, R1, R14, R15, R16, T7, T8, T10, T11, T14, T16 164 160
No Connect
# of Signal pins # of User I/O pins
84 80
84 80
120 116
164 160
OE (1,2) Global OE pins. GCLR Global Clear pin. GCLK (1,2,3) Global Clock pins. TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing. GNDINT Ground pins for the internal device logic. GNDIO Ground pins for the I/O drivers. VCCINT VCC pins for the internal device logic. VCCIO VCC pins for the I/O drivers.
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ATF1516AE(L)
2398E-12/01
ATF1516AE(L)
ATF1516AE(L) I/O Pinouts
MC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PLB A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 100-pin TQFP 2 1 100 99 98 8 7 6 5 4 100-ball BGA C1 B1 B2 A2 A3 D2 D1 D3 C2 A1 144-pin TQFP 2 1 143 142 141 140 139 10 9 8 7 6 5 4 208-pin PQFP 153 154 159 160 161 162 163 164 166 167 141 142 144 145 146 147 148 149 150 151 256-ball BGA C3 C4 E5 D5 C5 B4 A4 A5 D6 C6 F5 F2 E1 F4 F3 E2 D2 E3 E4 D4 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PLB C C C C C C C C C C C C C C C C D D D D D D D D D D D D D D D D 100-pin TQFP 25 24 23 22 21 31 30 29 28 27 100-ball BGA K1 J1 H1 H2 G2 H4 J3 K3 J2 K2 144-pin TQFP 36 35 34 32 31 30 29 28 44 43 42 41 40 39 38 37 208-pin PQFP 108 109 110 111 112 113 114 115 117 118 92 93 95 96 97 98 99 100 101 102 256-ball BGA N4 P3 N3 M4 M2 L4 L5 K6 K5 K4 N6 T5 M6 R5 M5 P5 N5 T4 R4 P4
57
2398E-12/01
ATF1516AE(L) I/O Pinouts
MC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PLB E E E E E E E E E E E E E E E E F F F F F F F F F F F F F F F F 100-pin TQFP 97 96 94 93 92 14 13 12 10 9 100-ball BGA B3 A4 B4 C4 C5 F4 E2 E1 E3 E4 144-pin TQFP 138 137 136 134 133 132 131 19 18 16 15 14 12 11 208-pin PQFP 168 169 170 171 172 173 175 176 177 178 130 131 132 133 135 136 137 138 139 140 256-ball BGA B6 E6 F7 E7 D7 C7 B7 A7 F8 B8 H5 H1 H2 H3 H4 G6 G5 G2 G4 F1 MC 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 PLB G G G G G G G G G G G G G G G G H H H H H H H H H H H H H H H H 100-pin TQFP 20 19 17 16 15 37 36 35 33 32 100-ball BGA G1 G3 F2 F1 F3 K5 J5 H5 K4 J4 144-pin TQFP 27 26 25 23 22 21 20 54 53 49 48 47 46 45 208-pin PQFP 119 120 121 122 123 124 126 127 128 129 79 80 81 84 86 87 88 89 90 91 256-ball BGA K3 K2 J7 H7 J5 J2 J3 J4 H6 J6 M8 N8 L8 R7 P7 N7 M7 L7 T6 R6
58
ATF1516AE(L)
2398E-12/01
ATF1516AE(L) I/O Pinouts
MC 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PLB I I I I I I I I I I I I I I I I J J J J J J J J J J J J J J J J 100-pin TQFP 80 81 83 84 85 63 64 65 67 68 100-ball BGA B8 A7 B7 C7 C6 F7 E9 E10 E8 E7 144-pin TQFP 114 116 117 118 119 120 121 122 90 91 92 93 94 96 97 208-pin PQFP 197 196 195 194 193 192 190 189 188 187 27 26 25 24 22 21 20 19 18 17 256-ball BGA C11 B11 A11 F10 E10 A10 C10 D10 F9 A9 J15 J16 J10 H14 H13 H12 H11 H10 G11 G14 MC 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 PLB K K K K K K K K K K K K K K K K L L L L L L L L L L L L L L L L 100-ball TQFP 57 58 60 61 62 40 41 42 44 45 100-pin BGA G10 G8 F9 F10 F8 K6 J6 H6 K7 J7 144-pin TQFP 82 83 84 86 87 88 89 55 56 60 61 62 63 65 208-pin PQFP 38 37 36 35 34 33 31 30 29 28 78 77 76 73 71 70 69 68 67 66 256-ball BGA K11 K12 K14 K13 K15 K16 J13 J14 J12 J11 R8 T9 R9 N9 M9 L9 R10 N10 M10 L10
59
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2398E-12/01
ATF1516AE(L) I/O Pinouts
MC 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 PLB M M M M M M M M M M M M M M M M N N N N N N N N N N N N N N N N 100-pin TQFP 75 76 77 78 79 69 70 71 72 73 100-ball BGA C10 B10 B9 A9 A8 D9 D10 D8 C9 A10 144-pin TQFP 106 107 108 109 110 111 112 113 98 99 100 101 102 103 104 208-pin PQFP 4 3 206 205 204 203 202 201 199 198 16 15 13 12 11 10 9 8 7 6 256-ball BGA B14 C13 B13 F12 E12 D12 C12 B12 E11 D11 G13 G12 F16 F15 F13 F14 E16 E14 E13 D13 MC 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 PLB O O O O O O O O O O O O O O O O P P P P P P P P P P P P P P P P 100-pin TQFP 52 53 54 55 56 46 47 48 49 50 100-ball BGA J10 H10 H9 J9 G9 H7 J8 K8 K9 K10 144-pin TQFP 74 75 77 78 79 80 81 66 67 68 69 70 71 72 208-pin PQFP 49 48 47 46 45 44 43 42 40 39 65 64 62 61 60 59 58 57 56 55 256-ball BGA R13 P13 N13 M14 M13 L13 L14 L12 L15 L16 R11 P11 N11 M11 T12 R12 M12 P12 N12 T13
60
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ATF1516AE(L)
ATF1516AE(L) Ordering Information
tPD (ns) 5.5 tCO1 (ns) 3.5 fMAX (MHz) 200 Ordering Code ATF1516AE-5 AC100 ATF1516AE-5 CTC100 ATF1516AE-5 AAC144 ATF1516AE-5 QC208 ATF1516AE-5 CTC256 ATF1516AE-7 AC100 ATF1516AE-7 CTC100 ATF1516AE-7 AAC144 ATF1516AE-7 QC208 ATF1516AE-7 CTC256 ATF1516AE-7 AI100 ATF1516AE-7 CTI100 ATF1516AE-7 AAI144 ATF1516AE-7 QI208 ATF1516AE-7 CTI256 10.0 6.4 100 ATF1516AE-10 AC100 ATF1516AE-10 CTC100 ATF1516AE-10 AAC144 ATF1516AE-10 QC208 ATF1516AE-10 CTC256 ATF1516AE-10 AI100 ATF1516AE-10 CTI100 ATF1516AE-10 AAI144 ATF1516AE-10 QI208 ATF1516AE-10 CTI256
15.0 9.0 77 ATF1508AEL-15 AC100 ATF1508AEL-15 CTC100 ATF1508AEL-15 AAC144 ATF1508AEL-15 QC208 ATF1508AEL-15 CTC256
Package 100A 100CT1 144AA 208Q1 256CT1 100A 100CT1 144AA 208Q1 256CT1 100A 100CT1 144AA 208Q1 256CT1 100A 100CT1 144AA 208Q1 256CT1 100A 100CT1 144AA 208Q1 256CT1
100A 100CT1 144AA 208Q1 256CT1
Operation Range Commercial (0C to 70C)
7.5
4.8
133
Commercial (0C to 70C)
Industrial (-40C to +85C)
Commercial (0C to 70C)
Industrial (-40C to +85C)
Commercial (0C to 70C)
Using "C" Product for Industrial
There is very little risk in using "C" devices for industrial applications because the VCC conditions for 3.3V products are the same for commercial and industrial (there is only 15C difference at the high end of the temperature range). To use commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type 100A 100CT1 144AA 208Q1 256CT1 100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP) 100-ball, Tape Ball Grid Array (TBGA) 1.0 mm pitch 144-lead, Low Profile Plastic Gull Wing Quad Flatpack (TQFP) 208-lead, Plastic Quad Flatpack (PQFP) 256-ball, Tape Ball Grid Array (TBGA) 1.0 mm pitch
61
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AC Characteristics ATF1532AE(L) (1)
AE -7 Symbol tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT(3) tACNT fACNT
(4)
AE -10 Min Max 10 10 7.6 0 3 0
AE -12 Min Max 12 12 9.1 0 3 0
AEL -15(6) Min Max 15 12 11 0 3 1 Unit ns ns ns ns ns MHz 9 5 5 5 4 ns ns ns ns ns 15 6 6 ns ns ns 13 70 ns MHz 13 70 66 ns MHz MHz 2 2 2 8 1 6 3.5 3 3 3 5 ns ns ns ns ns ns ns ns ns ns ns
Parameter Input or Feedback to Non-registered Output I/O Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
Min
Max 7.5 7.5
5.6 0 3 0 1 3 3 2.5 0.2 1 3 3 8.6 120 8.6 120 133 0.7 0.7 3.1 2.7 0.4 2.2 1.0 0 1.0 1.5 6.0 7.8 4.7
1 4 4 3.5 0.3 1 4 4
6.3
1 5 5 4.1 0.4
7.5
10.4
1 5 5
12.5
11.5 90 11.5 90 100 0.9 0.9 3.6 3.5 0.5 2.8 1.3 0 1.5 2.0 6.5 75 80 75
13.9
13.9
fMAX(5) tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3
1.0 1.0 4.1 4.4 0.6 3.5 3.5 0 1.7 2.2 6.7
tZX1
4
5
5
7
ns
62
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ATF1532AE(L)
AC Characteristics ATF1532AE(L) (Continued)(1)
AE -7 Symbol tZX2 tZX3 Parameter Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35pF) Output Buffer Disable Delay (CL= 5pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay 2.1 0.6 1.6 1.4 1.3 0.6 1.8 1.0 1.7 1.0 1.0 3.0 Min Max 4.5 9 AE -10 Min Max 5.5 10 AE -12 Min Max 5.5 10 AEL -15(6) Min Max 7 10 Unit ns ns
tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tRPA Notes:
(2)
4 3.0 0.8 1.6 1.4
5 3.5 1.0 1.6 1.4 1.7 0.8 2.3 1.3 2.2 1.4 1.4 4.0
5 5 4 2 2 2.1 1.0 2.9 1.7 2.7 1.7 4.8 4.8
6
ns ns ns ns ns
2 2 6 6 2 4 4 2
ns ns ns ns ns ns ns ns
Reduced Power Adder 4.5 5.0 5.0 10 ns 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipeline data. 6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical, the device will achieve the speeds of the -10 column. (See "ITD/automatic power down.")
63
2398E-12/01
ATF1532AE(L) Pinouts
144-lead TQFP - Top View
144 127 1 108
19
ATF1508AE(L) ATF1516AE(L) ATF1532AE(L)
90
36 54 72
208-lead PQFP - Top View
208 183
1
156
26
ATF1516AE(L) ATF1532AE(L)
131
64
ATF1532AE(L)
2398E-12/01
104
53
78
ATF1532AE(L)
ATF1532AE(L) 256-ball 1.0 mm Pitch Bottom View
A B C D E F G H J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
65
2398E-12/01
ATF1532AE(L) Dedicated Pinouts
Dedicated Pin INPUT/GCLK1 INPUT/GCLR INPUT/OE1 INPUT/OE2/GCK2 I/O/GCLK3 I/O PD (1,2) TDI (JTAG) TMS (JTAG) TCK (JTAG) TDO (JTAG) GNDINT GNDIO VCCINT VCCIO No Connect # of Signal pins # of User I/O pins 144-pin TQFP 125 127 126 128 TBD TBD 4 20 89 104 52, 57, 124, 129 3, 13, 17, 33, 59, 64, 85, 105, 135 51, 58, 123, 130 24, 50, 73, 76, 95, 115, 144 120 116 208-pin PQFP 184 182 183 181 TBD TBD 176 127 30 189 75, 82, 180, 185 14, 32, 50, 51, 94, 116, 134, 152, 158, 200 74, 83, 179, 186 5, 23, 41, 63, 85, 105, 107, 125, 143, 165, 191, 207 176 172 256-ball BGA D9 E8 E9 D8 TBD TBD D4 J6 J11 D13 A8, C9, G9, K8, P9 A3, B10, C2, D14, F6, G10, H8, J9, K7, L11, M3, P6, P10, R2, R3, T1, T15 B9, C8, G8, K9, P8 B3, B5, C14, E15, F11, G3, G7, G15, H9, J8, K10, L3, L6, M15, P14, T2, T3 212 206
OE (1,2) Global OE pins. GCLR Global Clear pin. GCLK (1,2,3) Global Clock pins. TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing. GNDINT Ground pins for the internal device logic. GNDIO Ground pins for the I/O drivers. VCCINT VCC pins for the internal device logic. VCCIO VCC pins for the I/O drivers.
66
ATF1532AE(L)
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ATF1532AE(L)
ATF1532AE(L) I/O Pinouts
MC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PLB A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 144-pin TQFP 134 133 132 131 138 137 136 208-pin PQFP 173 175 176 177 178 169 170 171 172 256-ball BGA D7 C7 B7 A7 F8 B8 D6 C6 B6 A6 F7 E7 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PLB C C C C C C C C C C C C C C C C D D D D D D D D D D D D D D D D 144-pin TQFP 142 141 140 139 2 1 143 208-pin PQFP 163 164 166 167 168 159 160 161 162 256-ball BGA E4 C5 A5 D5 E5 E6 B2 A2 B4 A4 C4 C3
67
2398E-12/01
ATF1532AE(L) I/O Pinouts
MC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PLB E E E E E E E E E E E E E E E E F F F F F F F F F F F F F F F F 144-pin TQFP 7 6 5 4 11 10 9 8 208-pin PQFP 153 154 155 156 157 147 148 149 150 151 256-ball BGA E3 C1 B1 A1 D2 D3 D4 F2 F3 F1 F4 E1 D1 E2 MC 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 PLB G G G G G G G G G G G G G G G G H H H H H H H H H H H H H H H H 144-pin TQFP 15 14 12 19 18 16 208-pin PQFP 141 142 144 145 146 135 136 137 138 139 140 256-ball BGA H6 G5 G4 G4 G1 G6 F5 J1 H7 H5 H2 H3 H1 H4
68
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ATF1532AE(L)
ATF1532AE(L) I/O Pinouts
MC 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PLB I I I I I I I I I I I I I I I I J J J J J J J J J J J J J J J J 144-pin TQFP 20 26 25 23 22 21 208-pin PQFP 129 130 131 132 133 122 123 124 126 127 128 256-ball BGA K1 J7 J6 J5 J4 J3 J2 L2 L1 K6 K5 K4 K3 K2 MC 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 PLB K K K K K K K K K K K K K K K K L L L L L L L L L L L L L L L L 144-pin TQFP 29 28 27 34 32 31 30 208-pin PQFP 115 117 118 119 120 121 109 110 111 112 113 114 256-ball BGA N4 M2 M1 M4 M5 L5 L4 R1 P2 N3 N2 P1 N1
69
2398E-12/01
ATF1532AE(L) I/O Pinouts
MC 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 PLB M M M M M M M M M M M M M M M M N N N N N N N N N N N N N N N N 144-pin TQFP 37 36 35 42 41 40 39 38 208-pin PQFP 101 102 103 104 106 108 95 96 97 98 99 100 256-ball BGA P5 N5 T4 R4 P4 P3 R6 T6 N6 M6 R5 T5 MC 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 PLB O O O O O O O O O O O O O O O O P P P P P P P P P P P P P P P P 144-pin TQFP 47 46 45 44 43 54 53 49 48 208-pin PQFP 88 89 90 91 92 93 79 80 81 84 86 87 256-ball BGA R7 P7 T7 L8 N7 M7 L7 M9 L9 R8 T8 N8 M8
70
ATF1532AE(L)
2398E-12/01
ATF1532AE(L)
ATF1532AE(L) I/O Pinouts
MC 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 PLB Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q R R R R R R R R R R R R R R R R 144-pin TQFP 55 56 60 61 62 63 65 208-pin PQFP 78 77 76 73 71 70 69 68 67 66 65 64 256-ball BGA N9 T9 R9 L10 M10 N10 R10 T10 M11 N11 P11 R11 T11 MC 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 PLB S S S S S S S S S S S S S S S S T T T T T T T T T T T T T T T T 144-pin TQFP 66 67 68 69 70 71 72 74 208-pin PQFP 62 61 60 59 58 57 56 55 54 53 52 49 256-ball BGA K11 M12 N12 T12 R12 T13 P12 T14 P13 R13 R14 R15
71
2398E-12/01
ATF1532AE(L) I/O Pinouts
MC 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 PLB U U U U U U U U U U U U U U U U V V V V V V V V V V V V V V V V 144-pin TQFP 75 77 78 79 80 81 208-pin PQFP 48 47 46 45 44 43 42 40 39 38 37 36 256-ball BGA P15 N15 T16 R16 P16 N14 N16 M14 N13 M16 M13 L14 L15 MC 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 PLB W W W W W W W W W W W W W W W W X X X X X X X X X X X X X X X X 144-pin TQFP 82 83 84 86 87 88 89 90 28 27 26 25 24 208-pin PQFP 35 34 33 31 30 29 256-ball BGA L16 L13 L12 K12 K14 K15 K16 J11 J12 J13 J14 J15 K13 J16
72
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ATF1532AE(L)
ATF1532AE(L) I/O Pinouts
MC 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 PLB Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 144-pin TQFP 91 92 93 94 96 97 208-pin PQFP 22 21 20 19 18 17 16 15 13 12 11 256-ball BGA H10 H11 H12 H15 H16 H14 H13 G12 G13 G14 G16 G11 F12 F13 MC 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 PLB AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB 144-pin TQFP 98 99 100 101 102 103 104 106 208-pin PQFP 10 9 8 7 6 4 3 2 1 208 256-ball BGA F14 F15 F16 E12 E13 E14 E16 D16 C16 B16 A16 D15 D13 C15
73
2398E-12/01
ATF1532AE(L) I/O Pinouts
MC 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 PLB CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD 144-pin TQFP 107 108 109 110 111 112 208-pin PQFP 206 205 204 203 202 201 199 198 197 256-ball BGA B15 A15 B14 A14 B13 A13 C13 D12 C12 B12 A12 E11 MC 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 PLB EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 144-pin TQFP 113 114 116 117 118 119 120 121 122 208-pin PQFP 196 195 194 193 192 190 189 188 187 256-ball BGA D11 C11 A11 B11 F10 E10 D10 C10 A10 J10 F9 A9
74
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ATF1532AE(L)
ATF1532AE(L) Ordering Information
tPD (ns) 7.5 tCO1 (ns) 4.7 fMAX (MHz) 133 Ordering Code ATF1532AE-7 AAC144 ATF1532AE-7 QC208 ATF1532AE-7 CTC256 ATF1532AE-10 AAC144 ATF1532AE-10 QC208 ATF1532AE-10 CTC256 ATF1532AE-10 AAI144 ATF1532AE-10 QI208 ATF1532AE-10 CTI256 12.0 7.5 80 ATF1532AE-12 AAC144 ATF1532AE-12 QC208 ATF1532AE-12 CTC256 ATF1532AE-12 AAI144 ATF1532AE-12 QI208 ATF1532AE-12 CTI256
15.0 9.0 66 ATF1508AEL-15 AAC144 ATF1508AEL-15 CC208 ATF1508AEL-15 CTC256
Package 144AA 208Q1 256CT1 144AA 208Q1 256CT1 144AA 208Q1 256CT1 144AA 208Q1 256CT1 144AA 208Q1 256CT1
144AA 169Q1 256CT1
Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to +85C) Commercial (0C to 70C) Industrial (-40C to +85C)
Commercial (0C to 70C)
10.0
6.3
100
Using "C" Product for Industrial
There is very little risk in using "C" devices for industrial applications because the VCC conditions for 3.3V products are the same for commercial and industrial (there is only 15C difference at the high end of the temperature range). To use commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type 144AA 208Q1 256CT1 144-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP) 208-ball, Plastic Quad Flatpack (PQFP) 256-lead, Tape Ball Grid Array (TBGA) 1.0 mm pitch
75
2398E-12/01
Atmel Headquarters
Corporate Headquarters
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(c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel (R) is the registered trademark of Atmel; Logic DoublingTM is the trademark of Atmel. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
2398E-12/01/0M

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